This invention relates to apparatus for programmed generation of timing signals and, in particular, programmable microprocessor-controlled pacemaker apparatus.
The evolution of pacemaker design has led to the incorporation of the microprocessor into the pacemaker apparatus, as a means for providing flexible programming of the pacemaker operation. The incorporation of a microprocessor into a cardiac pacer has been made possible by the development of a relatively low power single chip CPU. For example, the CDP 1802 employs CMOS technology, operates at relatively low power with a single power supply, and has a broad operating temperature range. For a pacemaker application, such a microprocessor is well suited for carrying out the desired sub-routines, interrupts and data access in general, and provides good capability for software control of the pacer operation. Even for a relatively simple modern day pacemaker, which operates only in one or a limited number of pacing modes, it is highly desirable to be able to program multiple parameters of the pacer operation, thus strongly indicating software control such as is provided by a microprocessor.
As is well known by those familiar with operation of microprocessors, the basic machine cycle and thus the speed of carrying out instructions is controlled by the rate of the clock pulses which establish the timing operation of the microprocessor. Further, for a CMOS microprocessor, power consumption is a direct function of the clock rate, the power drain being directly proportional to the clock rate due to the nature of CMOS switching. Thus, a tradeoff is presented as between the desire for a low power drain and the desire for a short instruction execution time, the latter requiring a high clock rate. Thus, to the extent it is compatible with carrying out the operating and house keeping functions required by the pacemaker, it is desired to minimize the clock rate so as to minimize power drain. Since normal pacing and natural heartbeat rates are in the order of 70 beats per minute, and the maximum allowable rate is usually set in the area of 120-150 per minute, more than sufficient time to carry out all microprocessor operations is available with a clock rate of 40 KHz, corresponding to a 25 microsecond clock interval. However, for the CDP 1802 each instruction requires 16 clock pulses, consisting of two 8-clock pulse machine cycles. Thus, a single instruction using this microprocessor takes 16 clock intervals, which equates to 400 microseconds for a 40 KHz clock. Thus, the minimum time unit for carrying out any software control operation is 400 microseconds, meaning that operations cannot be carried out with any greater time resolution. Indeed, most operations which incorporate communicating an output from the microprocessor require at least three such instructions, making the minimum resolution 1200 microseconds, or 1.2 ms. Thus, it is seen that for software controlled operations, operation of the clock generator at a relatively low frequency has the advantage of minimizing current drain, but this advantage is gained only with the relative loss of speed in carrying out desired operations.
More specifically, in the pacer application there is a need for generating signals which are time controlled, such as the periodic output stimulus pulse, blanking intervals, etc. Generation of these signals requires electronic circuits, suitably on a separate chip from the microprocessor, which are controlled by software generated outputs delivered at designated microprocessor output pins and connected to the control chip. In order to utilize the versatility of the microprocessor, it is desired that these signals be software controlled, i.e., generated by specific sub-routines as stored in memory associated with the microprocessor. However, if the minimum time unit within which the microprocessor program can operate is greater than time intervals for the output signals, there is a conflict between the application needs and the software capability. Also, if a sequence of output pulses is desired, the normal software is unable to control generation of such sequences without time gaps during which necessary microprocessor instructions are carried out. There is thus a need for a means of interfacing the microprocessor capability with the specific additional electronic circuitry of the pacer, in order to achieve the desired time responses necessary for the pacer application.